Backside clock mesh research featured in Semiconductor Engineering

Our new preprint, "Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology" by Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy, and Matthew R. Guthaus, was featured by Semiconductor Engineering. The work explores placing clock meshes on the backside metal layers of 2 nm nanosheet technologies with backside power delivery networks, which can cut clock skew and power. Congratulations to the authors!