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Prospective students: Please check out this information!

I’m a Professor at UC Santa Cruz in the area of chip design and electronic design automation (EDA). I’m the lead PI of the VLSI Design and Automation Lab as well as a member of the Hardware Systems Collective.

Our research sits at the intersection of chip design and electronic design automation (EDA). We focus on physical design, circuits, and algorithms research, including clock distribution, memory design, low-power circuits, variability and reliability. Recently, we have been at the forefront of applying machine learning and graph neural networks (GNNs) to EDA challenges, such as GATMesh and fast surrogate models for clock mesh timing analysis, GAT-Steiner for routing prediction, and GNN-based effective capacitance modeling. We are also exploring backside clock meshes for 2 nm nanosheet technologies and open-source two-phase clocking flows. We build open-source infrastructure for the community, including the OpenRAM and OpenGCRAM memory compilers and the HighTide benchmark suite of modern RTL-to-GDS designs. Our alumni go on to work at a variety of top chip design companies, including NVIDIA, Apple, Intel, Qualcomm, AMD, Altera, Oracle, and Cadence. View our publications for more details.