HOME

Prospective students: Please check out this information!

I’m a Professor at UC Santa Cruz in the area of chip design and electronic design automation (EDA). I’m the lead PI of the VLSI Design and Automation Lab as well as a member of the Hardware Systems Collective.

I founded the VLSI Design Automation (VLSI-DA) lab at UC Santa Cruz in Fall 2006. The primary research focus is on physical design, circuits, and algorithms research. Topics that have been investigated include design for low-power circuits, variability and reliability, thermal-aware design, and error tolerant circuit design.

Current Research: ML/GNN for EDA

Our lab is at the forefront of applying machine learning and graph neural networks (GNNs) to electronic design automation challenges. Recent research includes:

• GATMesh: Using graph neural networks for clock mesh timing analysis to improve accuracy and efficiency
• GAT-Steiner: Applying GNNs to predict optimal Rectilinear Steiner Minimal Trees for interconnect routing
• Effective Capacitance Modeling: Leveraging graph neural networks to model complex capacitance effects in modern chip designs
• OpenGCRAM: Developing an open-source gain cell compiler enabling design-space exploration optimized for AI workloads

These projects represent our commitment to advancing EDA through modern AI techniques, creating faster and more efficient design tools for next-generation chips. View our publications for more details.

Latest News