For my most recent publications, please see my Google Scholar profile.

2025

• Mapping Two Decades of Innovation: Lessons from 25 Years of ISPD Research
  G Rahmaniani, M Guthaus, L Behjat. Proceedings of the 2025 International Symposium on Physical Design, 102-110, 2025.

2024

• Vlsi hypergraph partitioning with deep learning
  MH Khan, B Onal, E Dogan, MR Guthaus. arXiv preprint arXiv:2409.01387, 2024.
• GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs
  B Onal, E Dogan, MH Khan, MR Guthaus. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided …, 2024.
• Open-Source Silicon—Unleashing Innovation and Collaboration
  M Guthaus, K Kim, F Brito-Filho, S Kawakami, B Murmann. IEEE Design and Test, 2024.

2023

• Openspike: an openram SNN accelerator
  F Modaresi, M Guthaus, JK Eshraghian. 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023.
• Sram design with openram in skywater 130nm
  J Cirimelli-Low, MH Khan, S Crow, A Lonkar, B Onal, AD Zonenberg, …. 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023.

2022

• NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report
  M Guthaus, C Batten, E Brunvand, PE Gaillardon, D Harris, R Manohar, …. https://nsf-ic-education.com/NSF_IC_Workshop_Final_Report.pdf, 2022.

2020

• Enabling design technology co-optimization of srams through open-source software
  M Guthaus, H Nichols, J Cirimelli-Low, J Kunzler, B Wu. 2020 IEEE International Electron Devices Meeting (IEDM), 41.7. 1-41.7. 4, 2020.
• System and method for a hybrid current-mode and voltage-mode integrated circuit
  M Guthaus, R Islam. US Patent 10,691,162, 2020.

2019

• Bottom-up approach for high speed sram word-line buffer insertion optimization
  B Wu, MR Guthaus. 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019.
• Automated synthesis of multi-port memories and control
  H Nichols, M Grimes, J Sowash, J Cirimelli-Low, MR Guthaus. 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019.
• Fast and area-efficient sram word-line optimization
  B Wu, JE Stine, MR Guthaus. 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019.
• Puffery: An Open-Source Benchmark Tool for PUFs
  H Nichols, MR Guthaus. .

2018

• HCDN: Hybrid-mode clock distribution networks
  R Islam, MR Guthaus. IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 251-262, 2018.
• DCMCS: Highly robust low-power differential current-mode clocking and synthesis
  R Islam, HA Fahmy, PY Lin, MR Guthaus. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018.
• Current-mode clock distribution
  M Guthaus, R Islam. US Patent 10,097,168, 2018.
• Distributed LC resonant tanks clock tree synthesis
  M Guthaus. US Patent 10,073,937, 2018.

2017

• Architectural opportunities for novel dynamic EMI shifting (DEMIS)
  DI Gorman, MR Guthaus, J Renau. Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017.
• Timing Speculative SRAM
  E Ebrahimi, M Guthaus, J Renau. International Symposium on Circuits and Systems (ISCAS), 2017.
• Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias
  R Sankaranarayanan, MR Guthaus. Proceedings of the Great Lakes Symposium on VLSI 2017, 431-434, 2017.
• Clock Design and Synthesis
  MR Guthaus. Electronic Design Automation for IC Implementation, Circuit Design, and …, 2017.
• Reducing Variability in Subthreshold Circuits
  R Sankaranarayanan. UC Santa Cruz, 2017.
• Current-Mode Clocking and Synthesis Considering Low-Power and Skew
  R Islam. University of California, Santa Cruz, 2017.

2016

• OpenRAM: An open-source memory compiler
  MR Guthaus, JE Stine, S Ataei, B Chen, B Wu, M Sarwar. 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016.
• A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS
  S Ataei, JE Stine, MR Guthaus. 2016 IEEE 34th international conference on computer design (ICCD), 499-506, 2016.
• CMCS: Current-mode clock synthesis
  R Islam, MR Guthaus. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3 …, 2016.
• Wafer masks, semiconductor device, and computer aided fabrication system for distributed LC resonant tanks and clock tree synthesis
  M Guthaus. US Patent 9,270,228, 2016.
• A 64 kb Differential Single-Port 12T SRAM Design With a Bit-Interleaving Scheme for Low
  S Ataei, JE Stine, MR Guthaus. .
• Том. 7-10-November-2016. 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016.-Сер. 2016 IEEE/ACM International Conference on Computer-Aided Design …
  S Chatterjee, FN Najm, V Sukharev, T Kim, Z Sun, C Cook, J Gaddipati, …. .

2015

• Circuit design for reliability
  R Reis, Y Cao, G Wirth. Springer New York, 2015.
• Low-power clock distribution using a current-pulsed clocked flip-flop
  R Islam, MR Guthaus. IEEE Transactions on Circuits and Systems I: Regular Papers 62 (4), 1156-1164, 2015.
• Differential current-mode clock distribution
  R Islam, H Fahmy, PY Lin, MR Guthaus. Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest …, 2015.
• Power-efficient multi-frequency resonant clock meshes
  M Guthaus. US Patent 9,143,086, 2015.
• LC resonant clock resource minimization using compensation capacitance
  PY Lin, HA Fahmy, R Islam, MR Guthaus. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1406-1409, 2015.
• Switched capacitor quasi-adiabatic clocks
  HA Fahmy, PY Lin, R Islam, MR Guthaus. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1398-1401, 2015.
• Systems and methods for integrated circuit C4 ball placement
  M Guthaus, S Logan. US Patent 8,966,427, 2015.
• Multi-frequency resonant clocks
  BM LaCara, PY Lin, MR Guthaus. Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 1402-1405, 2015.
• Differential Current-Mode Clock Distribution
  M Guthaus, R Islam, H Fahmy, PY Lin. .

2014

• Confronting the variability issues affecting the performance of next-generation SRAM design to optimize and predict the speed and yield
  J Samandari-Rad, M Guthaus, R Hughey. IEEE Access 2, 577-601, 2014.
• Current-mode clock distribution
  R Islam, MR Guthaus. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1203-1206, 2014.
• Distributed resonant clock grid synthesis
  M Guthaus, X Hu. US Patent 8,719,748, 2014.
• Methods for integrated circuit C4 ball placement
  M Guthaus. US Patent 8,782,585, 2014.
• Variability-Aware Clock Design
  MR Guthaus, G Wilke. Circuit Design for Reliability, 255-272, 2014.
• Current-mode clock distribution
  M Guthaus, R Islam. .
• Distributed LC resonant tanks clock tree synthesis
  M Guthaus. US Patent 8,739,100, 2014.

2013

• Revisiting automated physical synthesis of high-performance clock networks
  MR Guthaus, G Wilke, R Reis. ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (2 …, 2013.
• Redundant C4 power pin placement to ensure robust power grid delivery
  S Logan, MR Guthaus. 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013.
• VLSI-SoC: from algorithms to circuits and system-on-chip design
  A Coskun, M Guthaus, S Katkoori, R Reis. Springer, 2013.
• SEU-aware low-power memories using a multiple supply voltage array architecture
  S Kim, MR Guthaus. VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP …, 2013.
• Embedded Tutorial: Breaking the Dynamic Power Barrier using Distributed-LC Resonant Clocking
  MR Guthaus. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC …, 2013.
• A decap placement methodology for reducing joule heating and temperature in PSN interconnect
  S Logan, MR Guthaus. Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest …, 2013.
• A Decap Placement Methodology for Reducing Joule Heating and Temperature in PSN
  M Guthaus, S Logan. .
• Porting 180 nm Technology to OpenRAM
  B Chen, PY Lin, M Guthaus. .
• From Algorithms to Circuits and System-on-chip Design: Revised Selected Papers
  A Burg, A Coskun, M Guthaus, S Katkoori, R Reis. Springer, 2013.
• Thermal-aware CAD for modern integrated circuits
  S Logan. University of California, Santa Cruz, 2013.

2012

• Distributed LC resonant clock grid synthesis
  X Hu, MR Guthaus. IEEE Transactions on Circuits and Systems I: Regular Papers 59 (11), 2749-2760, 2012.
• High-performance clock mesh optimization
  MR Guthaus, X Hu, G Wilke, G Flach, R Reis. ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012.
• Library-aware resonant clock synthesis (LARCS)
  X Hu, W Condley, MR Guthaus. Proceedings of the 49th Annual Design Automation Conference, 145-150, 2012.
• VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS
  J Samandari-Rad, M Guthaus, R Hughey. Thirteenth International Symposium on Quality Electronic Design (ISQED), 506-515, 2012.
• High-performance, low-power resonant clocking
  MR Guthaus, B Taskin. Proceedings of the International Conference on Computer-Aided Design, 742-745, 2012.
• A single-VDD ultra-low energy sub-threshold FPGA
  R Sankaranarayanan, MR Guthaus. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012.
• Lithography-aware layout compaction
  C Andrus, MR Guthaus. Proceedings of the great lakes symposium on VLSI, 147-152, 2012.
• Dynamic voltage scaling for SEU-tolerance in low-power memories
  S Kim, MR Guthaus. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012.
• Harmonic resonant clocking
  HB Skinner, X Hu, M Guthaus. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012.
• Architecture for Increased Address Space in an Ultra-Low-Power Microprocessor
  B Redd, S Kellis, N Gaskin, M Guthaus, R Brown. Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest …, 2012.
• Welcome from the general chair
  MR Guthaus. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012.
• Analysis and application of inductance in clock distribution networks
  X Hu. University of California, Santa Cruz, 2012.
• Low-power methodology for fault tolerant nanoscale memory design
  S Kim. University of California, Santa Cruz, 2012.

2011

• Distributed LC resonant clock tree synthesis
  MR Guthaus. 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1215-1218, 2011.
• Distributed resonant clock grid synthesis (ROCKS)
  X Hu, M Guthaus. Proceedings of the 48th Design Automation Conference, 516-521, 2011.
• Package-chip co-design to increase flip-chip C4 reliability
  S Logan, MR Guthaus. 12th International Symposium on Quality Electronic Design (ISQED 2011), 2011.
• Low-power multiple-bit upset tolerant memory optimization
  S Kim, MR Guthaus. 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 577-581, 2011.
• A methodology for local resonant clock synthesis using LC-assisted local clock buffers
  WJ Condley, X Hu, MR Guthaus. 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 503-506, 2011.
• Leakage-aware redundancy for reliable sub-threshold memories
  S Kim, M Guthaus. Proceedings of the 48th Design Automation Conference, 435-440, 2011.
• SNM-aware power reduction and reliability improvement in 45nm SRAMs
  S Kim, MR Guthaus. 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 204-207, 2011.
• SET Susceptibility Analysis in Buffered Tree Clock Distribution Networks
  R Chipana, FL Kastensmidt, J Tonfat, R Reis, M Guthaus. Conference on Radiation Effects on Components and Systems (RADECS), 2011.
• Clock tree optimization for electromagnetic compatibility (EMC)
  X Hu, MR Guthaus. 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 184-189, 2011.
• Advanced logic design through hands-on digital music synthesis
  W Condley, AW Hill, MR Guthaus. 2011 IEEE International Conference on Microelectronic Systems Education, 17-20, 2011.

2010

• Non-uniform clock mesh optimization with linear programming buffer insertion
  MR Guthaus, G Wilke, R Reis. Proceedings of the 47th Design Automation Conference, 74-79, 2010.
• Analysis of high-performance clock networks with RLC and transmission line effects
  WJ Condley, X Hu, MR Guthaus. Proceedings of the 12th ACM/IEEE international workshop on System level …, 2010.
• Analysis of power supply induced jitter in actively de-skewed multi-core systems
  D Chan, MR Guthaus. 2010 11th International Symposium on Quality Electronic Design (ISQED), 785-790, 2010.

2009

• Fast thermal-aware floorplanning using white-space optimization
  S Logan, MR Guthaus. 2009 17th IFIP International Conference on Very Large Scale Integration …, 2009.
• Fault-tolerant synthesis using non-uniform redundancy
  KL Woo, MR Guthaus. 2009 IEEE International Conference on Computer Design, 213-218, 2009.
• Measuring and modeling variabilityusing low-cost FPGAs.
  M Brown, C Bazeghi, MR Guthaus, J Renau. FPGA, 286, 2009.
• Teaching VLSI design in 10 weeks
  MR Guthaus. 2009 IEEE International Conference on Microelectronic Systems Education, 41-44, 2009.

2008

• Clock tree synthesis with data-path sensitivity matching
  MR Guthaus, D Sylvester, RB Brown. 2008 Asia and South Pacific Design Automation Conference, 498-503, 2008.

2006

• Clock buffer and wire sizing using sequential programming
  MR Guthaus, D Sylvester, RB Brown. Proceedings of the 43rd annual Design Automation Conference, 1041-1046, 2006.
• Process-induced skew reduction in nominal zero-skew clock trees
  MR Guthaus, D Sylvester, RB Brown. Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006.
• Clock tree analysis and synthesis considering process parameters and variability
  MR Guthaus. University of Michigan, 2006.

2005

• Gate sizing using incremental parameterized statistical timing analysis
  MR Guthaus, N Venkateswaran, C Visweswariah, V Zolotov. Proceedings of the 2005 IEEE/ACM International conference on Computer-aided …, 2005.
• Partitioning variables across register windows to reduce spill code in a low-power processor
  RA Ravindran, RM Senger, ED Marsman, GS Dasika, MR Guthaus, …. IEEE Transactions on Computers 54 (8), 998-1012, 2005.
• A 16-bit low-power microcontroller with monolithic MEMS-LC clocking
  ED Marsman, RM Senger, MS McCorquodale, MR Guthaus, …. Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 624-627, 2005.
• Optimization objectives and models of variation for statistical gate sizing
  MR Guthaus, N Venkateswaran, V Zolotov, D Sylvester, RB Brown. Proceedings of the 15th ACM Great Lakes symposium on VLSI, 313-316, 2005.

2003

• A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference
  RM Senger, ED Marsman, MS McCorquodale, FH Gebara, KL Kraver, …. Proceedings of the 40th annual Design Automation Conference, 520-525, 2003.
• Increasing the number of effective registers in a low-power processor using a windowed register file
  RA Ravindran, RM Senger, ED Marsman, GS Dasika, MR Guthaus, …. Proceedings of the 2003 international conference on Compilers, architecture …, 2003.
• A low-power microinstrument for chemical analysis of remote environments
  S Martin, RM Senger, ED Marsman, FH Gebara, MS McCorquodale, …. 11th NASA Symp. on VLSI Design 1 (1), 1-4, 2003.
• Microsystem and SoC Design with UMIPS.
  MS McCorquodale, ED Marsman, RM Senger, FH Gebara, MR Guthaus, …. VLSI-SOC, 324-, 2003.
• BAE Systems mission specific processor technology
  D Rickard, R Berger, E Chan, B Clegg, S Patton, R Anderson, R Brown, …. GOMAC 3, 28th, 2003.

2001

• MiBench: A free, commercially representative embedded benchmark suite
  MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown. Proceedings of the fourth annual IEEE international workshop on workload …, 2001.

2000

• A mixed-signal sensor interface microinstrument
  KL Kraver, MR Guthaus, TD Strong, PL Bird, GS Cha, W Hoeld, RB Brown. Hilton Head Solid State Sensors and Actuators Workshop, 14-17, 2000.