For my most recent publications, please see my Google Scholar profile.

2024

• Bugra Onal, Eren Dogan, Muhammad Hadir Khan, Matthew R Guthaus, GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs, International Conference on Computer-Aided Design (ICCAD), October, 2024.

2023

• F. Modaresi, M. Guthaus, J. Eshraghian, OpenSpike: an OpenRAM SNN Accelerator, International Symposium on Circuits and Systems (ISCAS), May, 2023.

• J. Cirimelli-Low, M. Hadir Khan, S. Crow, A. Lonkar, B. Onal, A.~D. Zonenberg, M.~R. Guthaus, SRAM Design with OpenRAM in Skywater 130nm, International Symposium on Circuits and Systems (ISCAS), May, 2023.

2022

• Guthaus et al., NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report, 2022.

2021

• E. Dogan, H. F. Ugurdag, M. Guthaus, ``OpenCache: An Open-Source OpenRAM Based Cache Generator’', Workshop on Open-Source EDA Technologies (WOSET), November, 2021.

2020

• Enabling design technology co-optimization of srams through open-source software, M Guthaus, H Nichols, J Cirimelli-Low, J Kunzler, B Wu 2020 IEEE International Electron Devices Meeting (IEDM), 41.7. 1-41.7. 4

2019

• Riadul Islam, Matthew R. Guthaus, HCDN: Hybrid-Mode Clock Distribution Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1), 251-262, 2019.

• Bin Wu, James E. Stine, Matthew R. Guthaus, Fast and Area-Efficient SRAM Word-Line Optimization. ISCAS, 1-5, 2019.

• Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus, Automated Synthesis of Multi-Port Memories and Control. VLSI-SoC, 59-64, 2019.

• Bin Wu, Matthew R. Guthaus, Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. VLSI-SoC, 305-310, 2019.

2018

• Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus, DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 26(10), 2108-2117, 2018.

2017

• Rajsaktish Sankaranarayanan, Matthew R. Guthaus, Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. ACM Great Lakes Symposium on VLSI, 431-434, 2017.

• Daphne I. Gorman, Matthew R. Guthaus, Jose Renau, Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO, 774-785, 2017.

• Elnaz Ebrahimi 0001, Matthew R. Guthaus, Jose Renau, Timing speculative SRAM. ISCAS, 1-4, 2017.

• Riadul Islam, Matthew R. Guthaus, CMCS: Current-Mode Clock Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25(3), 1054-1062, 2017.

2016

• Samira Ataei, James E. Stine, Matthew R. Guthaus, A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. ICCD, 499-506, 2016.

• Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar, OpenRAM: an open-source memory compiler. ICCAD, 93, 2016.

2015

• Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus, Differential current-mode clock distribution. MWSCAS, 1-4, 2015.

• Riadul Islam, Matthew R. Guthaus, Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4), 1156-1164, 2015.

• Benjamin M. LaCara, Ping-Yao Lin, Matthew R. Guthaus, Multi-frequency resonant clocks. ISCAS, 1402-1405, 2015.

• Hany Ahmed Fahmy, Ping-Yao Lin, Riadul Islam, Matthew R. Guthaus, Switched capacitor quasi-adiabatic clocks. ISCAS, 1398-1401, 2015.

• Ping-Yao Lin, Hany Ahmed Fahmy, Riadul Islam, Matthew R. Guthaus, LC resonant clock resource minimization using compensation capacitance. ISCAS, 1406-1409, 2015.

2014

• Riadul Islam, Matthew R. Guthaus, Current-mode clock distribution. ISCAS, 1203-1206, 2014.

• Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey, Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield. IEEE Access 2, 577-601, 2014.

2013

• Sheldon Logan, Matthew R. Guthaus, Redundant C4 power pin placement to ensure robust power grid delivery. MWSCAS, 449-452, 2013.

• Sheldon Logan, Matthew R. Guthaus, A decap placement methodology for reducing joule heating and temperature in PSN interconnect. MWSCAS, 840-843, 2013.

• Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis 0001, Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. 18(2), 31:1-31:27, 2013.

• Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören 0001, Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC, 2013.

2012

• Xuchu Hu, Walter James Condley, Matthew R. Guthaus, Library-aware resonant clock synthesis (LARCS). DAC, 145-150, 2012.

• Seokjoong Kim, Matthew R. Guthaus, SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. VLSI-SoC (Selected Papers), 181-195, 2012.

• Curtis Andrus, Matthew R. Guthaus, Lithography-aware layout compaction. ACM Great Lakes Symposium on VLSI, 147-152, 2012.

• Matthew R. Guthaus, Baris Taskin, High-Performance, Low-Power Resonant Clocking: Embedded tutorial. ICCAD, 742-745, 2012.

• Xuchu Hu, Matthew R. Guthaus, Distributed LC Resonant Clock Grid Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11), 2749-2760, 2012.

• Matthew R. Guthaus, Welcome from the general chair. VLSI-SoC, 2012.

• Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus, Harmonic resonant clocking. VLSI-SoC, 59-64, 2012.

• Bennion Redd, Spencer S. Kellis, Nathaniel Gaskin, Matthew Guthaus, Richard Brown 0003, Architecture for increased address space in an ultra-low-power microprocessor. MWSCAS, 125-128, 2012.

• Jeren Samandari-Rad, Matthew R. Guthaus, Richard Hughey, VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS. ISQED, 506-515, 2012.

• Seokjoong Kim, Matthew R. Guthaus, Dynamic voltage scaling for SEU-tolerance in low-power memories. VLSI-SoC, 207-212, 2012.

• Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis 0001, High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3), 33:1-33:17, 2012.

• Rajsaktish Sankaranarayanan, Matthew R. Guthaus, A single-VDD ultra-low energy sub-threshold FPGA. VLSI-SoC, 219-224, 2012.

2011

• Walter James Condley, Andrew W. Hill, Matthew R. Guthaus, Advanced logic design through hands-on digital music synthesis. MSE, 17-20, 2011.

• Xuchu Hu, Matthew R. Guthaus, Clock tree optimization for Electromagnetic Compatibility (EMC). ASP-DAC, 184-189, 2011.

• Walter James Condley, Xuchu Hu, Matthew R. Guthaus, A methodology for local resonant clock synthesis using LC-assisted local clock buffers. ICCAD, 503-506, 2011.

• Matthew R. Guthaus, Distributed LC resonant clock tree synthesis. ISCAS, 1215-1218, 2011.

• Sheldon Logan, Matthew R. Guthaus, Package-chip co-design to increase flip-chip C4 reliability. ISQED, 553-558, 2011.

• Seokjoong Kim, Matthew R. Guthaus, Low-power multiple-bit upset tolerant memory optimization. ICCAD, 577-581, 2011.

• Seokjoong Kim, Matthew R. Guthaus, Leakage-aware redundancy for reliable sub-threshold memories. DAC, 435-440, 2011.

• Seokjoong Kim, Matthew R. Guthaus, SNM-aware power reduction and reliability improvement in 45nm SRAMs. VLSI-SoC, 204-207, 2011.

• Xuchu Hu, Matthew R. Guthaus, Distributed Resonant clOCK grid Synthesis (ROCKS). DAC, 516-521, 2011.

2010

• Walter James Condley, Xuchu Hu, Matthew R. Guthaus, Analysis of high-performance clock networks with RLC and transmission line effects. SLIP, 51-58, 2010.

• Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis 0001, Non-uniform clock mesh optimization with linear programming buffer insertion. DAC, 74-79, 2010.

• Derek Chan, Matthew R. Guthaus, Analysis of power supply induced jitter in actively de-skewed multi-core systems. ISQED, 785-790, 2010.

2009

• Matthew R. Guthaus, Teaching VLSI design in 10 weeks. MSE, 41-44, 2009.

• Keven L. Woo, Matthew R. Guthaus, Fault-tolerant synthesis using non-uniform redundancy. ICCD, 213-218, 2009.

• Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau, Measuring and modeling variabilityusing low-cost FPGAs. FPGA, 286, 2009.

2008

• Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Clock tree synthesis with data-path sensitivity matching. ASP-DAC, 498-503, 2008.

2006

• Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC, 84-89, 2006.

• Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown, Clock buffer and wire sizing using sequential programming. DAC, 1041-1046, 2006.

2005

• Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown, Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. IEEE Trans. Computers 54(8), 998-1012, 2005.

• Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov, Gate sizing using incremental parameterized statistical timing analysis. ICCAD, 1029-1036, 2005.

• Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown, Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI, 313-316, 2005.

2003

• Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown, A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. DAC, 520-525, 2003.

• Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown, Increasing the number of effective registers in a low-power processor using a windowed register file. CASES, 125-136, 2003.