HighTide
A diverse, actively maintained open-source VLSI benchmark suite spanning multiple design languages and technology nodes, built on the OpenROAD RTL-to-GDSII flow.
A diverse, actively maintained open-source VLSI benchmark suite spanning multiple design languages and technology nodes, built on the OpenROAD RTL-to-GDSII flow.
Existing benchmarks haven't kept pace with modern hardware diversity.
Evaluation of EDA tools, circuits, and systems often relies on outdated hardware benchmarks. Existing benchmark designs are predominantly RISC-V CPUs, providing limited representation of the diverse components found in modern heterogeneous SoCs—from ML accelerators and GPUs to cryptographic engines and networking cores.
The growing diversity of design languages poses an additional challenge. While designs exploiting the parameterization capabilities of Chisel, Python-based generators, and SystemVerilog are increasingly prevalent in the open-source community, the majority of benchmarks available to suites remain Verilog-only snapshots—often never updated after their initial release.
For designs actively receiving upstream updates, relying on stale static snapshots risks producing results that no longer reflect a design's true complexity and structure. Models trained on a narrow design set learn patterns specific to those designs, rather than generalizable circuit behaviors. HighTide addresses these gaps with a benchmark suite that evolves alongside the open-source hardware ecosystem.
Processors, accelerators, cryptographic engines, and networking cores—not just CPUs. Cell counts range from under 20k to over 1M.
Designs originating from Verilog, SystemVerilog, Chisel, Python (LiteX), and migen, compiled down to Verilog for physical implementation.
Git submodules track upstream sources. Updates are summarized and applied with AI-assisted Claude Code skills.
End-to-end RTL-to-GDSII benchmarks exercising synthesis, floorplanning, placement, CTS, routing, and sign-off—not just point-tool targets.
Infrastructure designed for reproducibility, scalability, and continuous evolution.
Targets ASAP7 (7nm), NanGate45 (45nm), and SKY130HD (130nm) technology nodes, enabling cross-node design exploration and tool evaluation.
Leverages OpenROAD-flow-scripts and the OpenROAD toolchain for an open, reproducible RTL-to-GDSII flow. Designs run within a Docker image by default, eliminating manual tool installation.
Bazel-ORFS integration partitions the flow into separate build targets, enabling incremental re-execution and remote caching to drastically reduce runtimes for large designs.
Tagged Git releases provide stable, versioned snapshots while regularly incorporating upstream changes through Git submodules for reproducible evaluation.
Diverse designs with varying structural composition—sequential-heavy, combinational-heavy, macro-dense—provide rich training data for ML-driven EDA research.
Fully open-source and designed to grow. Contribute new designs, improve existing configurations, or use the suite for your research.
Hardware blocks typically found in commercial heterogeneous SoCs.
| Design | Description | Language | Platforms |
|---|---|---|---|
| BlackParrot | RISC-V multicore processor (unicore & quad core variants) | SystemVerilog | asap7 nangate45 sky130hd |
| Gemmini | Systolic array matrix multiplication accelerator | Chisel | asap7 nangate45 sky130hd |
| SHA3 | SHA-3 cryptographic hash accelerator | Chisel | asap7 nangate45 sky130hd |
| CNN | Convolutional neural network accelerator | Python (NNgen/Veriloggen) | asap7 nangate45 sky130hd |
| Eyeriss v2 | Sparse CNN accelerator (2×2 cluster array) | Verilog | asap7 nangate45 sky130hd |
| NyuziProcessor | GPGPU-style multicore vector processor | SystemVerilog | asap7 nangate45 |
| Minimax | Minimal area RISC-V core (serially-fetched) | Verilog | asap7 nangate45 sky130hd |
| LiteDRAM | Configurable DRAM controller (SDR PHY, AXI+WB+native frontend) | Python (Migen/LiteX) | asap7 nangate45 sky130hd |
| LiteEth | Lightweight Ethernet core (UDP / Xilinx UltraScale+ GTH SGMII) | Python (Migen/LiteX) | asap7 nangate45 sky130hd |
| LitePCI | Lightweight PCIe endpoint (kcu105 / Xilinx UltraScale+ pcie_us hard-IP) | Python (Migen/LiteX) | asap7 nangate45 |
| CoralNPU | Google Coral neural processing unit accelerator | Chisel | asap7 nangate45 sky130hd |
| NVDLA | NVIDIA Deep Learning Accelerator (5 partitions) | Verilog | asap7 nangate45 sky130hd |
| FlooNoC | PULP Platform 4x4 mesh network-on-chip | SystemVerilog | asap7 nangate45 |
| Snitch Cluster | PULP Platform energy-efficient compute cluster | SystemVerilog | asap7 |
| Ternip | SystemVerilog ternary matmul inference accelerator | SystemVerilog | asap7 nangate45 sky130hd |
| Vortex | Open-source RISC-V GPGPU | SystemVerilog | asap7 nangate45 sky130hd |
Placement views illustrating the structural diversity across the suite—from small combinational datapaths to large systolic arrays and macro-dense accelerators.
Bazel-ORFS partitions the RTL-to-GDSII flow into incremental build targets with remote caching for fast rebuilds and reproducible baseline results.
Baseline results for all designs are cached remotely. After tracking an upstream update, Bazel re-executes only the stages whose inputs changed, drastically reducing rebuild times for large designs.
Claude Code skills that automate discovery, integration, optimization, and debugging of benchmark designs.
HighTide includes a set of Claude Code skills—AI-powered slash commands that automate the complex, multi-step processes involved in managing a benchmark suite. These skills handle everything from searching the open-source hardware ecosystem for new candidates, to performing full RTL-to-GDSII integration, to debugging flow failures and optimizing PPA—reducing what would take hours of manual work to a single command.
Searches the open-source hardware ecosystem for designs that would strengthen the benchmark suite, evaluates them against HighTide's selection criteria, and opens GitHub issues to propose additions.
/find-designs accelerators)Performs the full end-to-end process of adding a new open-source hardware design to the suite, from submodule setup through RTL generation to flow configuration and testing.
Audits all designs and tool dependencies for upstream updates, summarizes what changed, and applies updates while maintaining flow compatibility.
Analyzes and diagnoses failures at any stage of the RTL-to-GDSII flow, from synthesis errors to routing congestion, with visual layout analysis.
Iteratively maximizes cell utilization and clock frequency while maintaining a clean flow with zero DRC violations.
Ports an existing design from one technology platform to another, adapting constraints, SRAM macros, and flow parameters for the target node.
Get up and running in minutes with the Bazel flow.
You need Bazelisk and Docker on an Ubuntu machine.
# Install Bazelisk
sudo apt install perl
sudo wget -O /usr/local/bin/bazel \
https://github.com/bazelbuild/bazelisk/releases/latest/download/bazelisk-linux-amd64
sudo chmod +x /usr/local/bin/bazelInitialize the bazel-orfs submodule after cloning — the build won't resolve targets without it.
git clone https://github.com/VLSIDA/HighTide.git
cd HighTide
git submodule update --init bazel-orfsRun the full RTL-to-GDSII flow for any design.
# Build a single design
bazel build //designs/asap7/lfsr:lfsr_final
# Build all designs for a platform
bazel build //designs/asap7/...
# Build everything
bazel build //designs/...Check build summaries and QoR reports.
./tools/summary.shSee the latest build results for detailed QoR metrics across all designs and platforms.